39 lines
493 B
Verilog
39 lines
493 B
Verilog
/*
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* Based on bug report pr772.
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*/
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module err ();
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parameter kuku = "AAAAA";
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reg reset_b,clk;
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initial begin
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reset_b = 0;
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repeat (10) @(posedge clk);
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#1 reset_b = 1;
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end
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initial begin
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clk = 1'b1;
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#3 forever #10 clk=~clk;
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end
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always @(posedge clk or negedge reset_b)
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if (!reset_b) begin
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end
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else begin
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if ((kuku=="RRRRR") || (kuku=="AAAAA") || (kuku=="BBBBB"))
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$display("PASSED");
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else $display("FAILED");
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$finish;
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end
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endmodule
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