20 lines
363 B
Verilog
20 lines
363 B
Verilog
/* From PR#722
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* If bounds checking is in a 16bit field, this will crash.
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*/
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module test;
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reg [65536 : 0] mem;
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integer i;
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initial begin
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i = 65536;
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mem[i] = 1;
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if (mem[i] !== 1) begin
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$display ("FAILED -- bit %0d (%b)", i, mem[i]);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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