34 lines
509 B
Verilog
34 lines
509 B
Verilog
/*
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* Based on Request id 1313366 in the iverilog Bugs database, or
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* pr699 in the ivl-bugs database.
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*/
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module bug;
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wire a, b, c, d;
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assign c = 1'b0;
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assign a = 1'b0;
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assign b = 1'b0;
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assign d = c ? a : b;
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initial
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begin
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force b = 1'b1;
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#1 if (b !== 1'b1) begin
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$display("FAILED -- b = %b", b);
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$finish;
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end
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if (d !== 1'b1) begin
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$display("FAILED -- d = %b", d);
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$finish;
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end
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release b;
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$display("PASSED");
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$finish;
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end
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endmodule // bug
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