32 lines
700 B
Verilog
32 lines
700 B
Verilog
module test(CLK, OE, A, OUT);
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parameter numAddr = 1;
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parameter numOut = 1;
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parameter wordDepth = 2;
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parameter MemFile = "ivltests/pr690.dat";
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input CLK, OE;
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input [numAddr-1:0] A;
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output [numOut-1:0] OUT;
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reg [numOut-1:0] memory[wordDepth-1:0];
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reg [numAddr-1:0] addr;
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initial begin
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// The whole point of this regression test is to check that
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// the file name argument can be a string parameter.
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$readmemb(MemFile,memory, 0);
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if (memory[0] !== 0) begin
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$display("FAILED -- memory[0] == %b", memory[0]);
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$finish;
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end
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if (memory[1] !== 1) begin
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$display("FAILED -- memory[1] == %b", memory[1]);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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