45 lines
923 B
Verilog
45 lines
923 B
Verilog
module test (clk, in, out);
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input clk;
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input [15:0] in;
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output [4:0] out;
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reg [4:0] out;
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(* ivl_synthesis_on *)
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always @(posedge clk) begin
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// In PR#685, this caused an assertion with iverilog -S
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out = (in >= 16) ? 16 : in;
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end
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endmodule
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module main;
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reg clk;
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reg [15:0] value;
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wire [4:0] sat;
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test dut (clk, value, sat);
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(* ivl_synthesis_off *)
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initial begin
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value = 0;
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clk = 1;
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for (value = 0 ; value < 'h15 ; value = value+1) begin
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#1 clk = 0;
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#1 clk = 1;
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#1 if ((value > 16) && (sat !== 5'd16)) begin
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$display("FAILED -- value=%d, sat=%b", value, sat);
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$finish;
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end
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if ((value <= 16) && (value !== sat)) begin
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$display("FAILED -- value=%d, sat=%b", value, sat);
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$finish;
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end
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end // for (value = 0 ; value < 'h15 ; value = value+1)
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$display("PASSED");
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end // initial begin
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endmodule // main
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