46 lines
978 B
Verilog
46 lines
978 B
Verilog
module main();
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parameter INIT_00 = 32'hffffffff;
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reg [17:0] t;
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reg [8:0] c;
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reg error ;
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initial begin
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error = 0;
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c = 0;
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$display("%b",INIT_00[c]);
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c = 1;
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$display("%b",INIT_00[c]);
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t = {17'd0,INIT_00[0]}<<1;
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if(t !== 17'b0_0000_0000_0000_0010)
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begin
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$display("FAILED - shift operation {17'd0,INIT_00[0]}<<1; %b",t);
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error = 1;
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end
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else
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$display("%b",t);
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c = 0;
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t = {17'd0,INIT_00[c]}<<1;
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if(t !== 17'b0_0000_0000_0000_0010)
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begin
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$display("FAILED - shift operation {17'd0,INIT_00[c]}<<1 %b",t);
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error = 1;
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end
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else
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$display("%b",t);
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c = 16;
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t = {17'd0,INIT_00[c]}<<1;
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if(t !== 17'b0_0000_0000_0000_0010)
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begin
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$display("FAILED - shift operation {17'd0,INIT_00[c]}<<1 %b",t);
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error = 1;
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end
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else
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$display("%b",t);
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if(error == 1)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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