24 lines
391 B
Verilog
24 lines
391 B
Verilog
/*
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* Based on PR#585.
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*/
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module main();
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reg [7:0] ram_temp;
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reg mem;
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initial begin
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ram_temp = 8'h08;
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mem = (ram_temp & 8'h08) >> 3;
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$write("Calculated: %b\nActually in mem: %b\n",((ram_temp & 8'h08) >> 3),
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mem);
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if (mem !== 1'b1) begin
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$display("FAILED == mem = %b", mem);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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