29 lines
632 B
Verilog
29 lines
632 B
Verilog
module module1(clock,reset,result);
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input clock,reset;
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output result;
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reg result;
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always @ (posedge clock)
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if (reset) result <= 0; else result <= 1;
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endmodule
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// driver
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module main;
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reg clk,reset;
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reg data[1:3]; // ILLEGAL port connection NOT detected
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// to fix, use wire data_1,data_2,data_3;
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module1 inst1(clk,reset,data[1]);
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module1 inst2(clk,reset,data[2]);
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module1 inst3(clk,reset,data[3]);
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always #50 clk = ~clk;
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initial begin
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$monitor($time,"clk=%b,reset=%b,%b%b%b",clk,reset,data[1],data[2],data
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[3]);
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clk = 0;
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reset = 1;
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#200 reset = 0;
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#200 $display("driver timeout"); $finish;
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end
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endmodule
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