17 lines
348 B
Verilog
17 lines
348 B
Verilog
/*
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* Derived from PR#569
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*/
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module test();
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parameter foo = 8'b01010101;
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parameter bar = {foo,{2{foo}}}; // fails
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// parameter tmp = {2{foo}}; // this + next line succeed
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// parameter bar = {foo,tmp};
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reg[23:0] cnt;
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reg CLK;
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initial $monitor("%b", cnt);
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initial CLK = 0;
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initial cnt = bar;
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endmodule
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