28 lines
1.0 KiB
Verilog
28 lines
1.0 KiB
Verilog
module example;
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wire y;
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reg p01, p01g, s01, s01g;
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bufif1 (pull0, pull1 ) ( y, p01, p01g );
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bufif1 (strong0, strong1) ( y, s01, s01g );
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initial begin
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$monitor( "%T Pu:%b/%b St:%b/%b Y:%b,%v",
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$time, p01, p01g, s01, s01g, y, y );
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{ p01, p01g, s01, s01g } = 4'b0000;
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#100 { p01, p01g, s01, s01g } = 4'b0x00;
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#100 { p01, p01g, s01, s01g } = 4'b000x;
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#100 { p01, p01g, s01, s01g } = 4'b1x00;
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#100 { p01, p01g, s01, s01g } = 4'b001x;
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#100 { p01, p01g, s01, s01g } = 4'b0100;
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#100 { p01, p01g, s01, s01g } = 4'b0001;
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#100 { p01, p01g, s01, s01g } = 4'b1100;
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#100 { p01, p01g, s01, s01g } = 4'b0011;
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#100 { p01, p01g, s01, s01g } = 4'bx100;
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#100 { p01, p01g, s01, s01g } = 4'b00x1;
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#100 { p01, p01g, s01, s01g } = 4'b010x;
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#100 { p01, p01g, s01, s01g } = 4'bx10x;
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#100 { p01, p01g, s01, s01g } = 4'b111x;
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#100 { p01, p01g, s01, s01g } = 4'bx11x;
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#100 ;
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end
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endmodule
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