43 lines
624 B
Verilog
43 lines
624 B
Verilog
module top;
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integer fail;
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reg cmd, reset;
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initial begin
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#1;
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reset = 0;
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fail = 0;
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#1;
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cmd = 0;
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#2;
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reset = 1;
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#2;
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cmd = 1;
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#2;
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cmd = 0;
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#2;
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reset = 0;
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#2;
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reset = 1;
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#4;
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if(fail) $display("***** disable test FAILED *****");
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else $display("***** disable test PASSED *****");
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$finish(0);
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end
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always @(cmd) begin: command_block
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fork
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begin
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#0; // avoid fork race
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disable command_block_reset;
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end
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begin: command_block_reset
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@(reset);
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fail = 1;
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disable command_block;
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end
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join
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end
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endmodule
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