65 lines
2.4 KiB
Verilog
65 lines
2.4 KiB
Verilog
module example;
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reg [3:0] mem [0:7];
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reg [3:0] addr;
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wire [3:0] m0 = mem[0];
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wire [3:0] m1 = mem[1];
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wire [3:0] m2 = mem[2];
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wire [3:0] m3 = mem[3];
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wire [3:0] m4 = mem[4];
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wire [3:0] m5 = mem[5];
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wire [3:0] m6 = mem[6];
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wire [3:0] m7 = mem[7];
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wire [3:0] maddr = mem[addr];
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initial begin
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$write( " " );
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$display(
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"time addr maddr m0 m1 m2 m3 m4 m5 m6 m7" );
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$write( " " );
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$display(
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"---- ---- ----- ---- ---- ---- ---- ---- ---- ---- ----" );
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$monitor( "%T %b %b %b %b %b %b %b %b %b %b",
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$time, addr, maddr,
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m0, m1, m2, m3, m4, m5, m6, m7 );
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mem[0] = 8;
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mem[1] = 1;
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mem[2] = 2;
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mem[3] = 3;
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mem[4] = 4;
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mem[5] = 5;
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mem[6] = 6;
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mem[7] = 7;
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addr = 0; // 0
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#100 addr = 1; // 100
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#100 addr = 2; // 200
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#100 addr = 3; // 300
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#100 addr = 4; // 400
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#100 addr = 5; // 500
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#100 addr = 6; // 600
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#100 addr = 7; // 700
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#100 addr = 8; // 800
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#100 addr = 4'b001x; // 900
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#100 addr = 4'b01x0; // 1000
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#100 addr = 4'b0x01; // 1100
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#100 addr = 0; // 1200
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#100 mem[addr] <= 9; // 1300
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#100 addr = 3; // 1400
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#100 mem[addr] <= 10; // 1500
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#100 addr = 6; // 1600
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#100 mem[addr] <= 11; // 1700
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#100 addr = 8; // 1800
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#100 mem[addr] <= 12; // 1900
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#100 addr = 4'b010x; // 2000
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#100 mem[addr] <= 13; // 2100
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#100 addr = 4'b00x1; // 2200
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#100 mem[addr] <= 14; // 2300
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#100 addr = 4'b0x10; // 2400
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#100 mem[addr] <= 15; // 2500
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#100 addr = 4'bxxxx; // 2600
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#100 mem[addr] <= 0; // 2700
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#100 $display( "Finish at time %T", $time );
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end
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endmodule
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