83 lines
2.4 KiB
Verilog
83 lines
2.4 KiB
Verilog
// Icarus 0.6 AND snapshot 20020728
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// -----------------------------
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// (1) force to nets not supported
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// (2) comment the force statement and the release statement will cause
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// the compiler to fail silently (no messages, no a.out)
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//
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// Icarus snapshot 20020817
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// ------------------------
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// Runs fine IFF the whole of a bus is set, cannot force individual bits
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// (Fails with a rather incomprehensible error)
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//
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// To run this, incant:
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// iverilog tt.v
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// (adding -Wall doesn't help)
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// vvp a.out (if a.out is generated!)
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//
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//
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// Veriwell
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// ---------
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// Runs fine IFF the whole of a bus is set, cannot force individual bits
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// & crashes if a release of an individual bit is attempted.
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//
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// To run this, incant:
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// veridos tt.v (or use the GUI)
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//
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module top ();
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reg [31:0] ii;
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reg fail;
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reg [1:0] a;
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wire [1:0] junk = a;
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wire [1:0] junkbus = a;
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initial begin
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a = 2'b01;
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#5; a = 2'b10;
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#10; a = 2'b11;
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end
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initial begin
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#2;
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force junk = 0;
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force junkbus[0] = 0;
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#10;
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release junk;
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#5;
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release junkbus[0];
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end
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initial begin
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$display("");
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$display("expecting junk,junkbus to be 1 at T=1");
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$display("then changing to 0 at T=2");
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$display("then junk is 0 from T=3 to T=11, while");
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$display("junkbus changes to 2 at T=5 and remains 2 through to T=16");
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$display("junk changes to 2 at T=12");
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$display("then 2 from T=13 to T=14");
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$display("then changing to 3 at T=15");
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$display("then 3 from T=16 on");
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$display("junkbus changes to 3 at T=17 and remains 3 from then on");
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$display("");
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for(ii = 0; ii < 20; ii = ii + 1) begin
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#0; // avoid race
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// junk
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if((ii == 1) && (junk !== 1)) fail = 1;
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if((ii > 2) && (ii < 12) && (junk !== 0)) fail = 1;
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if((ii > 12) && (ii < 14) && (junk !== 2'b10)) fail = 1;
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if((ii > 15) && (junk !== 2'b11)) fail = 1;
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// junkbus
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if((ii == 1) && (junkbus !== 2'b01)) fail = 1;
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if((ii > 2) && (ii < 4) && (junkbus !== 2'b00)) fail = 1;
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if((ii > 5) && (ii < 17) && (junkbus !== 2'b10)) fail = 1;
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if((ii > 17) && (junkbus !== 2'b11)) fail = 1;
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$display("time: %0t, a: %b, junk: %b, junkbus: %b",$time,a,junk,junkbus);
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#1;
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end
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if(fail) $display("\n\t--------- force test failed ---------\n");
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else $display("\n\t--------- force test passed ---------\n");
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end
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endmodule
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