29 lines
465 B
Verilog
29 lines
465 B
Verilog
primitive passthrough (o, i);
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input i;
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output o;
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table
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// i : o
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1 : 1;
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0 : 0;
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? : 0;
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endtable
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endprimitive
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module test;
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reg i;
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wire o1, o1b, o2, o2b;
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initial begin
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i = 1'b0;
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#1;
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if ((o1 !== 1'b0) && (o1b !== 1'b1) &&
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(o2 !== 1'b0) && (o2b !== 1'b1)) $display("FAILED");
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else $display("PASSED");
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end
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passthrough (o1, i);
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passthrough (o1b, !i);
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passthrough (o2, i);
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passthrough (o2b, ~i);
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endmodule
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