39 lines
448 B
Verilog
39 lines
448 B
Verilog
module pr3534333();
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/* Check compiler accepts null statements in blocks */
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integer count = 0;
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initial begin
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end
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initial begin
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(* my_attr = 0 *) ;
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end
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initial begin
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(* my_attr = 0 *) ;
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#1 count = count + 1;
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end
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initial begin
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#2 count = count + 1;
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(* my_attr = 0 *) ;
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end
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initial begin
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;
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#3 count = count + 1;
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;
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end
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initial begin
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#4;;
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if (count === 3)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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