22 lines
346 B
Verilog
22 lines
346 B
Verilog
module top;
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reg a, b, c, d, e;
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wand out;
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assign out = a;
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assign out = b;
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assign out = c;
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assign out = d;
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assign out = e;
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initial begin
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a = 1'b1;
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b = 1'b0;
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c = 1'b1;
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d = 1'b1;
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e = 1'b1;
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#1;
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if (out !== 1'b0) $display("FAILED: expected 1'b1, got %b", out);
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else $display("PASSED");
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end
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endmodule
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