41 lines
762 B
Verilog
41 lines
762 B
Verilog
module tb;
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reg [1:0] i, j;
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reg [3:0] x;
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reg error;
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initial begin
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error = 0;
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i = 0;
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j = i++;
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if (i !== 2'b01 || j !== 2'b00) begin
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$display("FAILED j = i++ --> j=%b, i=%b", j, i);
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error = 1;
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end
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i = 0;
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x[0] = 1'bx;
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x[1] = 1'bx;
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x[0] = 1'b0;
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if (x[0] !== 1'b0 || x[1] !== 1'bx) begin
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$display("FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b", x[0], x[1], i);
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error = 1;
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end
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i = 0;
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x[0] = 1'b1;
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x[0] += 1'b1;
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if (x[0] !== 1'b0) begin
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$display("FAILED x[0] should be 0, but it is %b.", x[0]);
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error = 1;
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end
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if (i !== 2'd0) begin
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$display("FAILED i should be 1, but it is %d.", i);
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error = 1;
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end
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if (error == 0)
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$display("PASSED");
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end
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endmodule // tb
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