25 lines
393 B
Verilog
25 lines
393 B
Verilog
module main;
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reg [1:0] x;
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reg [2:0] y;
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initial begin
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x = 1;
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y = {1'b0, x << 1};
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if (y !== 3'b010) begin
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$display("FAILED -- y (%b) != 3'b010", y);
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$finish;
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end
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y = {1'b0, x << 2};
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if (y !== 3'b000) begin
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$display("FAILED -- y (%b) != 3'b000", y);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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