31 lines
659 B
Verilog
31 lines
659 B
Verilog
module top;
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reg pass;
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reg [7:0] val;
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reg signed [7:0] sval;
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initial begin
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pass = 1'b1;
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// An unsized number has an implicit width of integer width.
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val = $unsigned(-4);
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if (val !== 8'hfc) begin
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$display("Failed unsigned, expected 8'hfc, got %h", val);
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pass = 1'b0;
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end
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val = $unsigned(-4'sd4);
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if (val !== 8'h0c) begin
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$display("Failed sized unsigned, expected 8'h0c, got %h", val);
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pass = 1'b0;
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end
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sval = $signed(4'hc);
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if (sval !== -4) begin
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$display("Failed signed, expected -4, got %d", sval);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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