29 lines
517 B
Verilog
29 lines
517 B
Verilog
module top;
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parameter param = -1;
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reg passed;
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wire [3:0] val = 11;
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wire [3:0] res = val + param;
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reg [3:0] rgval = 11;
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reg [3:0] rgres;
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initial begin
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passed = 1'b1;
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#1;
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if (res !== 10) begin
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$display("FAILED wire result, expected 10, got %d", res);
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passed = 1'b0;
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end
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rgres = rgval + param;
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if (rgres !== 10) begin
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$display("FAILED reg result, expected 10, got %d", rgres);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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