56 lines
1.3 KiB
Verilog
56 lines
1.3 KiB
Verilog
/*
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* Copyright (c) 2001 Philip Blundell
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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primitive p (Q, D);
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input D;
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output Q;
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reg Q;
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initial Q = 1'b0;
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table
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0 : ? : 0;
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1 : ? : 1;
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endtable
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endprimitive
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module m;
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reg D;
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wire Q;
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reg A;
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wire QQ;
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p(Q, D);
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buf(QQ, Q);
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initial
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begin
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// The #1 is needed here to allow the initial values to
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// settle. Without it, there is a time-0 race.
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#1 $display(QQ, Q);
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#10
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D = 0;
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#15
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$display(QQ, Q);
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#20
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D = 1;
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#25
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$display(QQ, Q);
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$finish(0);
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end
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endmodule
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