49 lines
1.3 KiB
Verilog
49 lines
1.3 KiB
Verilog
// Verify that a zero width signal replication is handled correctly.
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module top;
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reg pass;
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reg [31:0] in_full;
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wire [31:0] pa_out_full, ca_out_full;
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reg [29:0] in_part;
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wire [31:0] pa_out_part, ca_out_part;
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initial begin
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pass = 1'b1;
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in_full = {16{2'b10}};
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in_part = {15{2'b01}};
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#1;
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if (pa_out_full !== 32'b10101010101010101010101010101010) begin
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$display("Failed: pa_out_full, got %b", pa_out_full);
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pass = 1'b1;
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end
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if (ca_out_full !== 32'b10101010101010101010101010101010) begin
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$display("Failed: ca_out_full, got %b", ca_out_full);
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pass = 1'b1;
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end
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if (pa_out_part !== 32'bxx010101010101010101010101010101) begin
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$display("Failed: pa_out_part, got %b", pa_out_part);
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pass = 1'b1;
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end
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if (ca_out_part !== 32'bzz010101010101010101010101010101) begin
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$display("Failed: ca_out_part, got %b", ca_out_part);
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pass = 1'b1;
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end
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if (pass) $display("PASSED");
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end
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param #(32) full(pa_out_full, ca_out_full, in_full);
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param #(30) part(pa_out_part, ca_out_part, in_part);
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endmodule
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module param #(parameter width = 32) (
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output reg [31:0] pa_out,
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output wire [31:0] ca_out,
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input [width-1:0] in);
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wire z_pad = 1'bz;
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wire x_pad = 1'bx;
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assign ca_out = {{32-width{z_pad}}, in};
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always @* pa_out = {{32-width{x_pad}}, in};
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endmodule
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