45 lines
1014 B
Verilog
45 lines
1014 B
Verilog
module top;
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reg [6:0] ltl;
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reg signed [6:0] ltl_s;
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reg [15:0] big;
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reg result, pass;
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initial begin
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pass = 1'b1;
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// An unsigned value should be zero padded.
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ltl = 7'd127;
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result = test(ltl);
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if (result) begin
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$display("Failed: unsigned argument was sign extended");
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pass = 1'b0;
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end
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// This should be evaluated in an eight bit context since the
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// function argument is eight bits. This will set the eight bit.
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result = test(ltl+7'd1);
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if (!result) begin
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$display("Failed: function width does not determines expression width.");
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pass = 1'b0;
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end
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// A signed value should be sign padded.
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ltl_s = -7'd1;
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result = test(ltl_s);
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if (!result) begin
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$display("Failed: signed argument was not sign extended");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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function test ;
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input signed [7:0] in;
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begin
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if (in[7]) test = 1'b1;
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else test = 1'b0;
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end
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endfunction
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endmodule
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