71 lines
1.6 KiB
Verilog
71 lines
1.6 KiB
Verilog
module cast_large_real;
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reg [63:0] u64;
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reg signed [63:0] i64;
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reg [64:0] u65;
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reg signed [64:0] i65;
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real r;
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reg fail;
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initial begin
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fail = 0;
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u64 = {1'b1, 63'd0};
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r = u64;
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$display("Convert u64 to real");
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$display("Expect : %0f", 2.0**63);
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$display("Got : %0f", r);
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if (r != 2.0**63) fail = 1;
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u64 = r;
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$display("Convert real to u64");
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$display("Expect : %0d", {1'b1, 63'd0});
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$display("Got : %0d", u64);
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if (u64 != {1'b1, 63'd0}) fail = 1;
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i64 = {1'b1, 63'd0};
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r = i64;
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$display("Convert i64 to real");
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$display("Expect : %0f", -(2.0**63));
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$display("Got : %0f", r);
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if (r != -(2.0**63)) fail = 1;
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i64 = r;
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$display("Convert real to i64");
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$display("Expect : %0d", $signed({1'b1, 63'd0}));
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$display("Got : %0d", i64);
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if (i64 != {1'b1, 63'd0}) fail = 1;
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u65 = {1'b1, 64'd0};
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r = u65;
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$display("Convert u65 to real");
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$display("Expect : %0f", 2.0**64);
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$display("Got : %0f", r);
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if (r != 2.0**64) fail = 1;
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u65 = r;
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$display("Convert real to u65");
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$display("Expect : %0d", {1'b1, 64'd0});
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$display("Got : %0d", u65);
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if (u65 != {1'b1, 64'd0}) fail = 1;
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i65 = {1'b1, 64'd0};
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r = i65;
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$display("Convert i65 to real");
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$display("Expect : %0f", -(2.0**64));
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$display("Got : %0f", r);
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if (r != -(2.0**64)) fail = 1;
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i65 = r;
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$display("Convert real to i65");
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$display("Expect : %0d", $signed({1'b1, 64'd0}));
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$display("Got : %0d", i65);
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if (i65 != {1'b1, 64'd0}) fail = 1;
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if (fail)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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