14 lines
398 B
Verilog
14 lines
398 B
Verilog
module top;
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reg [3:0] array [0:1];
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initial begin
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$dumpfile("work/pr2859628.vcd");
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$dumpvars(0, top);
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// This will complain that the array words have already been included!
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// They have not been since array words are only explicitly added.
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// The word/scope check code needs to be updated to ignore array words.
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$dumpvars(0, array[0], array[1]);
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#1;
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end
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endmodule
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