45 lines
1.2 KiB
Verilog
45 lines
1.2 KiB
Verilog
// A zero value MCD should be allowed, but does it process the arguments?
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module top;
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integer mcd, test;
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initial begin
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test = 0;
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// Skipped, but function is called.
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#1;
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$display($stime);
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mcd = 0;
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$fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd);
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$fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1));
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$fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1));
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#1;
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$display($stime);
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mcd = 1;
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$fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd);
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$fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1));
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$fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1));
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$fflush(mcd);
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// Skipped, but function is called.
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#1;
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$display($stime);
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mcd = 0;
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$fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd);
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$fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1));
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$fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1));
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#1;
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$display($stime);
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if (test != 6) $display("FAILED side effect test");
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else $display("PASSED");
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end
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function integer my_func;
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input incr;
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begin
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test = test + incr;
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my_func = test;
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end
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endfunction
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endmodule
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