49 lines
968 B
Verilog
49 lines
968 B
Verilog
//`timescale 1ns/1ps
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module test;
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reg c1reg,c2reg;
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pulldown (weak0) pd1 (r1a,r1c,r1o);
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pulldown (weak0) pd2 (r2a,r2c,r2o);
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pulldown pd (r1a);
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pullup pu (r2a);
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wire c1 = c1reg;
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wire c2 = c2reg;
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SPDT_RELAY r1 (.COIL1(c1), .COIL2(c2), .ARM(r1a), .NC(r1c), .NO(r1o));
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SPDT_RELAY r2 (.COIL1(c1), .COIL2(c2), .ARM(r2a), .NC(r2c), .NO(r2o));
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initial
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begin
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c1reg = 0;
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c2reg = 0;
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repeat (16)
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begin
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c1reg = 1;
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#10;
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c1reg = 0;
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#10;
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end
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$display ("%t: Test passed.",$realtime);
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$display ("PASSED");
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$finish;
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end
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endmodule
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module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO);
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inout COIL1, COIL2, ARM, NC, NO;
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wire coil = ((COIL1===1'b1) && (COIL2===1'b0)) || ((COIL1===1'b0) && (COIL2===1'b1));
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wire #1 dly_coil = coil;
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wire coil_on = coil & dly_coil;
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wire coil_off = !coil & !dly_coil;
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//assign NC = (coil_off) ? ARM : 1'bz;
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//assign NO = (coil_on) ? ARM : 1'bz;
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tranif1 t1 (ARM,NC,coil_off);
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tranif1 t2 (ARM,NO,coil_on);
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endmodule
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