63 lines
1.2 KiB
Verilog
63 lines
1.2 KiB
Verilog
`timescale 1ns/1ps
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module top;
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reg pass;
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reg ina, inb;
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wire out;
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my_or dut(out, ina, inb);
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initial begin
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pass = 1'b1;
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ina = 1'b0;
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inb = 1'b0;
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#0.399
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if (out !== 1'bx && out !== 1'bz) begin
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$display("FAILED: gate had incorrect delay, expected x/z, got %b.", out);
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pass = 1'b0;
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end
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#0.002
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if (out !== 1'b0) begin
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$display("FAILED: gate had incorrect delay, expected 0, got %b.", out);
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pass = 1'b0;
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end
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// Check inertial delays.
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ina = 1'b1;
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#0.399
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ina = 1'b0;
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#0.002
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if (out !== 1'b0) begin
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$display("FAILED: inertial delay, expected 0, got %b.", out);
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pass = 1'b0;
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end
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// Check that this change is relative to the first edge.
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ina = 1'b1;
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#0.200;
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inb = 1'b1;
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#0.201;
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if (out !== 1'b1) begin
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$display("FAILED: double edge delay, expected 1, got %b.", out);
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pass = 1'b0;
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#0.200;
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if (out === 1'b1) begin
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$display("FAILED: double edge delay was off second edge.");
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end
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end
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if (pass) $display("PASSED");
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end
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endmodule
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module my_or(out, ina, inb);
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output out;
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input ina, inb;
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or(out, ina, inb);
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specify
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(ina, inb *> out) = 0.4;
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endspecify
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endmodule
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