121 lines
3.1 KiB
Verilog
121 lines
3.1 KiB
Verilog
module top;
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reg in1, in2, pass, checkc, checkg, checkp;
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wire outc, outg, outp;
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assign #400 outc = in1 | in2;
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or #400 g1(outg, in1, in2);
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my_or #400 g2(outp, in1, in2);
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initial begin
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// $monitor($time,,outc, outg, outp,, in1,, in2);
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pass = 1'b1;
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checkc = 1'b0;
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checkg = 1'b0;
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checkp = 1'b0;
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in1 = 1'b0;
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in2 = 1'b0;
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#100 in1 = 1'b1;
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#200 in2 = 1'b1;
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#199;
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// Check to see if the output changed early.
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if (outc !== 1'bz && outc !== 1'bx) begin
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$display("CA output changed early!");
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pass = 1'b0;
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end
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if (outg !== 1'bz && outg !== 1'bx) begin
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$display("Gate output changed early!");
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pass = 1'b0;
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end
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if (outp !== 1'bz && outp !== 1'bx) begin
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$display("UDP output changed early!");
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pass = 1'b0;
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end
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#2;
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// Check to see if the output changed late.
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if (outc !== 1'b1) begin
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$display("CA output changed late!");
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pass = 1'b0;
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checkc = 1'b1;
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end
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if (outg !== 1'b1) begin
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$display("Gate output changed late!");
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pass = 1'b0;
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checkg = 1'b1;
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end
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if (outp !== 1'b1) begin
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$display("UDP output changed late!");
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pass = 1'b0;
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checkp = 1'b1;
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end
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#198;
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// We need to execute the three if checks in parallel.
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fork
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if (checkc) begin
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if (outc === 1'bz || outc === 1'bx) begin
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#2;
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// Check to see if the output changed off of the wrong edge.
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if (outc === 1'b1)
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$display("CA output triggered off of in2 change instead of in1.");
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else
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$display("CA output triggered very late.");
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end
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end
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if (checkg) begin
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if (outg === 1'bz || outg === 1'bx) begin
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#2;
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// Check to see if the output changed off of the wrong edge.
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if (outg === 1'b1)
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$display("Gate output triggered off of in2 change instead of in1.");
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else
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$display("Gate output triggered very late.");
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end
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end
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if (checkp) begin
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if (outp === 1'bz || outp === 1'bx) begin
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#2;
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// Check to see if the output changed off of the wrong edge.
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if (outp === 1'b1)
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$display("UDP output triggered off of in2 change instead of in1.");
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else
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$display("UDP output triggered very late.");
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end
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end
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#2; // This keeps the passing case alligned with the fails.
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join
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// Generate a 399 wide negative pulse that should be skipped.
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in1 = 1'b0;
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in2 = 1'b0;
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#399;
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in1 = 1'b1;
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in2 = 1'b1;
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#2;
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// Check that the pulse did not propagate.
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if (outc !== 1'b1) begin
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$display("CA does not have inertial delay.");
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pass = 1'b0;
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end
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if (outg !== 1'b1) begin
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$display("Gate does not have inertial delay.");
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pass = 1'b0;
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end
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if (outp !== 1'b1) begin
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$display("UDP does not have inertial delay.");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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primitive my_or (out, in1, in2);
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output out;
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input in1, in2;
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table
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0 0 : 0;
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1 ? : 1;
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? 1 : 1;
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endtable
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endprimitive
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