58 lines
1.3 KiB
Verilog
58 lines
1.3 KiB
Verilog
module top;
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parameter a_res = 16'b000001xx0xxx0xxx;
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parameter o_res = 16'b01xx1111x1xxx1xx;
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parameter x_res = 16'b01xx10xxxxxxxxxx;
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reg pass;
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reg [15:0] y, z, a, o, x;
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reg [127:0] yl, zl, al, ol, xl;
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initial begin
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pass = 1'b1;
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y = 16'b01xz01xz01xz01xz;
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z = 16'b00001111xxxxzzzz;
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yl = {8{y}};
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zl = {8{z}};
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// Check the & results
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a = y & z;
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if (a !== a_res) begin
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$display("FAILED: & test, expected %b, got %b", a_res, a);
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pass = 1'b0;
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end
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al = yl & zl;
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if (al !== {8{a_res}}) begin
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$display("FAILED: & (large) test, expected %b, got %b", {8{a_res}}, al);
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pass = 1'b0;
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end
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// Check the | results
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o = y | z;
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if (o !== o_res) begin
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$display("FAILED: | test, expected %b, got %b", o_res, o);
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pass = 1'b0;
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end
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ol = yl | zl;
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if (ol !== {8{o_res}}) begin
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$display("FAILED: | (large) test, expected %b, got %b", {8{o_res}}, ol);
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pass = 1'b0;
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end
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// Check the ^ results
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x = y ^ z;
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if (x !== x_res) begin
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$display("FAILED: | test, expected %b, got %b", x_res, x);
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pass = 1'b0;
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end
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xl = yl ^ zl;
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if (xl !== {8{x_res}}) begin
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$display("FAILED: ^ (large) test, expected %b, got %b", {8{x_res}}, xl);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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