31 lines
896 B
Verilog
31 lines
896 B
Verilog
module top;
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// The array code does not currently work because we need &APV<>!
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// Both &PV<> and &APV<> (when implemented) need to have bit
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// specific value change callbacks to function correctly.
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reg [7:0] array [1:0];
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reg [7:0] bs, ps;
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integer idx;
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initial begin
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bs = 8'b0;
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ps = 8'b0;
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array[0] = 8'b0;
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$monitor($time," BS = ", bs[1], ", PS = ", ps[2:1], ", AR = ", array[0][1]);
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// This should only trigger the $monitor when bit 1 changes.
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for (idx = 0; idx < 8 ; idx = idx + 1) begin
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#1 bs[idx] = 1'b1;
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end
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// This should only trigger the $monitor when bit 1 or 2 changes.
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for (idx = 0; idx < 8 ; idx = idx + 1) begin
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#1 ps[idx] = 1'b1;
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end
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// This should only trigger the $monitor when bit 1 of array[0] changes..
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for (idx = 0; idx < 8 ; idx = idx + 1) begin
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#1 array[0][idx] = 1'b1;
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end
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end
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endmodule
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