47 lines
1.0 KiB
Verilog
47 lines
1.0 KiB
Verilog
`timescale 1ns/1ns
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module sum_test;
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reg clk;
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wire [10:0] s;
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initial begin
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clk = 0;
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forever #10 clk = ~clk;
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end
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sum #(5, 8) sum (clk, {8'd10,8'd20,8'd30,8'd40,8'd50}, s);
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initial begin
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$display("Starting...");
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repeat (50) @(posedge clk);
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$display("sum = %d",s);
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if (s !== 150)
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$display("FAILED: expected 150, received %0d",s);
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else
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$display("PASSED");
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$finish;
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end
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endmodule
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module sum
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#(
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parameter n = 4,
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parameter width = 8,
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parameter log_n = $clog2(n)
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)
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(
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input clk,
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input [n*width-1:0]addends,
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output reg [log_n+width-1:0] s
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);
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// This should fail at the first recursion since this is not inside
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// a generate block.
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wire [$clog2(n/2)+width-1:0] a1;
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wire [$clog2(n-n/2)+width-1:0] a2;
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sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1);
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sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2);
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always @(posedge clk) s <= a1 + a2;
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endmodule // sum
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