49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
module top;
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reg pass;
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reg [7:0] a, b;
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wire [15:0] ruu, rsu, rus, rss;
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reg signed [15:0] res;
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integer i;
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assign ruu = a % b;
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assign rsu = $signed(a) % b;
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assign rus = a % $signed(b);
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assign rss = $signed(a) % $signed(b);
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initial begin
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pass = 1'b1;
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// Run 1000 random vectors
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for (i = 0; i < 1000; i = i + 1) begin
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// Random vectors
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a = $random;
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b = $random;
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#1;
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// Check unsigned % unsigned.
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if (ruu !== a%b) begin
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$display("FAILED: u%%u (%b%%%b) gave %b, expected %b", a, b, ruu, a%b);
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pass = 1'b0;
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end
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// Check signed % unsigned division.
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if (rsu !== a%b) begin
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$display("FAILED: s%%u (%b%%%b) gave %b, expected %b", a, b, rsu, a%b);
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pass = 1'b0;
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end
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// Check unsigned % signed division.
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if (rus !== a%b) begin
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$display("FAILED: u%%s (%b%%%b) gave %b, expected %b", a, b, rus, a%b);
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pass = 1'b0;
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end
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// Check signed % signed division.
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res = $signed(a)%$signed(b);
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if (rss !== res) begin
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$display("FAILED: s%%s (%b%%%b) gave %b, expected %b", a, b, rss, res);
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pass = 1'b0;
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end
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end
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if (pass) $display("PASSED");
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end
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endmodule
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