58 lines
1.4 KiB
Verilog
58 lines
1.4 KiB
Verilog
// Check that the >> and >>> operators with unsigned values.
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module top;
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parameter py = 8'b10101010 >> 3'b101;
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parameter pz = 8'b10101010 >>> 3'b101;
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reg passed;
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reg [7:0] a;
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reg [2:0] b;
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wire [7:0] wy, wz;
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reg [7:0] ry, rz;
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// Check CA code.
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assign wy = a >> b;
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assign wz = a >>> b;
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initial begin
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passed = 1'b1;
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// Example vector
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a = 8'b10101010;
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b = 3'b101;
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#1;
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// Check the parameter results.
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if (py !== 8'b00000101) begin
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$display("Failed param. >>, expected 8'b00000101, got %b", py);
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passed = 1'b0;
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end
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if (pz !== 8'b00000101) begin
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$display("Failed param. >>>, expected 8'b00000101, got %b", pz);
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passed = 1'b0;
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end
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// Check the procedural results.
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ry = a >> b;
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if (ry !== 8'b00000101) begin
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$display("Failed procedural >>, expected 8'b00000101, got %b", ry);
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passed = 1'b0;
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end
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rz = a >>> b;
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if (rz !== 8'b00000101) begin
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$display("Failed procedural >>>, expected 8'b00000101, got %b", rz);
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passed = 1'b0;
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end
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// Check the CA results.
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if (wy !== 8'b00000101) begin
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$display("Failed CA >>, expected 8'b00000101, got %b", wy);
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passed = 1'b0;
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end
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if (wz !== 8'b00000101) begin
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$display("Failed CA >>>, expected 8'b00000101, got %b", wz);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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