34 lines
1021 B
Verilog
34 lines
1021 B
Verilog
module top;
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reg [39:0] x, x_inv_bug, temp_x;
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integer i, j;
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wire [39:0] res2 = {40 {1'd1}} / x;
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initial begin
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// Using this assignment instead of the procedural assignment below
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// will work with out asserting.
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// x = 1;
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// assign x_inv_bug = {40 {1'd1}} / x;
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temp_x = 2**31;
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for (i=30 ; i < 38; i=i+1) begin
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temp_x = temp_x << 1;
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for (j=0 ; j<3; j=j+1) begin
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x = temp_x + (j-1);
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$display(" // i,j,temp_x,x => %2d,%1d,%d,%h", i, j, temp_x, x);
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// The following statement is asserting and it looks to be a
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// problem in the division algorithm. This specific case is
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// likely only a 32 bit problem, but by scaling I'm sure this
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// could be made to trigger on a 64 bit machine.
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x_inv_bug = {40 {1'd1}} / x;
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#1 $display("x_inv_bug=%h, res2=%h", x_inv_bug, res2);
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if (x_inv_bug !== res2) begin
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$display("FAILED");
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$finish;
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end
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end
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end // for (i=30 ; i < 38; i=i+1)
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$display("PASSED");
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end
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endmodule
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