43 lines
791 B
Verilog
43 lines
791 B
Verilog
// We want to print a warning if we find a delay that comes from the
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// default timescale (1s) and then one from a given timescale.
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// Basically we want to have either the case of no timescales or
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// timescales for all delays.
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module wo_time(out, in);
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output out;
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input in;
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buf(out, in);
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specify
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(in => out) = 1;
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endspecify
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endmodule
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module top;
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reg in;
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wire out_wo, out_w;
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wo_time wo(out_wo, in);
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w_time w(out_w, in);
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initial begin
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in = 1'b1;
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#2 $finish(0);
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end
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always @(out_wo) $display("The time in wo_time is: %e", $abstime);
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always @(out_w) $display("The time in w_time is: %e", $abstime);
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endmodule
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`timescale 1ns/1ns
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module w_time(out, in);
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output out;
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input in;
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buf(out, in);
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specify
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(in => out) = 1;
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endspecify
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endmodule
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