38 lines
842 B
Verilog
38 lines
842 B
Verilog
module top;
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reg pass = 1'b1;
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parameter one = 1'b1;
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parameter zero = 1'b0;
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parameter udef = 1'bx;
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real rl1 = one ? 4 : 4.5; // 4.0
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real rl2 = zero ? 4.0 : 5; // 5.0
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real rl3 = udef ? 6 : 6.0; // 6.0
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real rl4 = udef ? 7 : 7; // 7.0
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initial begin
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#1;
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if (rl1 != 4.0) begin
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$display("FAILED: real expression one, expected 4.0, got %f", rl1);
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pass = 1'b0;
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end
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if (rl2 != 5.0) begin
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$display("FAILED: real expression two, expected 5.0, got %f)", rl2);
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pass = 1'b0;
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end
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if (rl3 != 6.0) begin
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$display("FAILED: real expression three, expected 6.0, got %f", rl3);
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pass = 1'b0;
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end
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if (rl4 != 7.0) begin
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$display("FAILED: real expression four, expected 7.0, got %f", rl4);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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