36 lines
1.2 KiB
Verilog
36 lines
1.2 KiB
Verilog
module top;
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lower #(1, 2, 3) dut();
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endmodule
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module lower;
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parameter one = 1; // This should be 'sd1
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parameter two = 2; // This should be 'sd2
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parameter three = 0; // This should be 'sd3
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parameter local1 = one - two; // This should be -'sd1
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parameter local_lt0 = local1 < 0; // This should be 'd1
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parameter local_le0 = local1 <= 0; // This should be 'd1
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parameter local_gt0 = local1 > 0; // This should be 'd0
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parameter local_ge0 = local1 >= 0; // This should be 'd0
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parameter local_0lt = 0 < local1; // This should be 'd1
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parameter local_0le = 0 <= local1; // This should be 'd1
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parameter local_0gt = 0 > local1; // This should be 'd0
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parameter local_0ge = 0 >= local1; // This should be 'd0
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reg err;
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initial begin
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err = 0;
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if (!local_lt0) err = 1;
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if (!local_le0) err = 1;
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if ( local_gt0) err = 1;
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if ( local_ge0) err = 1;
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if ( local_0lt) err = 1;
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if ( local_0le) err = 1;
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if (!local_0gt) err = 1;
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if (!local_0ge) err = 1;
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if (err == 0) $display("PASSED");
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else $display("FAILED");
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end
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endmodule
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