29 lines
453 B
Verilog
29 lines
453 B
Verilog
module test ();
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parameter t=0;
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reg t_not, t_zero;
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generate
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if (!t) begin
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initial t_not = 1;
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end
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endgenerate
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generate
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if (t==0) begin
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initial t_zero = 1;
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end
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endgenerate
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initial begin
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#1 if (t_not !== 1) begin
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$display("FAILED -- t_not=%b", t_not);
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$finish;
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end
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if (t_zero !== 1) begin
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$display("FAILED -- t_zero=%b", t_zero);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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