140 lines
4.2 KiB
Verilog
140 lines
4.2 KiB
Verilog
module top;
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reg passed;
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parameter zero = 1'b0;
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parameter one = 1'b1;
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parameter highz = 1'bz;
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parameter undef = 1'bx;
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initial begin
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passed = 1'b1;
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if (&zero !== 1'b0) begin
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$display("FAILED const. reduction & with input 1'b0, expected 1'b0, ",
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" got %b", &zero);
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passed = 1'b0;
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end
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if (&one !== 1'b1) begin
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$display("FAILED const. reduction & with input 1'b1, expected 1'b1, ",
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" got %b", &one);
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passed = 1'b0;
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end
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if (&highz !== 1'bx) begin
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$display("FAILED const. reduction & with input 1'bz, expected 1'bx, ",
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" got %b", &highz);
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passed = 1'b0;
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end
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if (&undef !== 1'bx) begin
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$display("FAILED const. reduction & with input 1'bx, expected 1'bx, ",
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" got %b", &undef);
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passed = 1'b0;
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end
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if (|zero !== 1'b0) begin
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$display("FAILED const. reduction | with input 1'b0, expected 1'b0, ",
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" got %b", |zero);
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passed = 1'b0;
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end
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if (|one !== 1'b1) begin
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$display("FAILED const. reduction | with input 1'b1, expected 1'b1, ",
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" got %b", |one);
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passed = 1'b0;
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end
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if (|highz !== 1'bx) begin
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$display("FAILED const. reduction | with input 1'bz, expected 1'bx, ",
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" got %b", |highz);
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passed = 1'b0;
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end
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if (|undef !== 1'bx) begin
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$display("FAILED const. reduction | with input 1'bx, expected 1'bx, ",
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" got %b", |undef);
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passed = 1'b0;
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end
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if (^zero !== 1'b0) begin
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$display("FAILED const. reduction ^ with input 1'b0, expected 1'b0, ",
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" got %b", ^zero);
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passed = 1'b0;
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end
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if (^one !== 1'b1) begin
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$display("FAILED const. reduction ^ with input 1'b1, expected 1'b1, ",
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" got %b", ^one);
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passed = 1'b0;
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end
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if (^highz !== 1'bx) begin
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$display("FAILED const. reduction ^ with input 1'bz, expected 1'bx, ",
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" got %b", ^highz);
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passed = 1'b0;
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end
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if (^undef !== 1'bx) begin
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$display("FAILED const. reduction ^ with input 1'bx, expected 1'bx, ",
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" got %b", ^undef);
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passed = 1'b0;
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end
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if (~&zero !== 1'b1) begin
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$display("FAILED const. reduction ~& with input 1'b0, expected 1'b1, ",
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" got %b", ~&zero);
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passed = 1'b0;
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end
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if (~&one !== 1'b0) begin
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$display("FAILED const. reduction ~& with input 1'b1, expected 1'b0, ",
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" got %b", ~&one);
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passed = 1'b0;
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end
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if (~&highz !== 1'bx) begin
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$display("FAILED const. reduction ~& with input 1'bz, expected 1'bx, ",
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" got %b", ~&highz);
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passed = 1'b0;
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end
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if (~&undef !== 1'bx) begin
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$display("FAILED const. reduction ~& with input 1'bx, expected 1'bx, ",
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" got %b", ~&undef);
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passed = 1'b0;
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end
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if (~|zero !== 1'b1) begin
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$display("FAILED const. reduction ~| with input 1'b0, expected 1'b1, ",
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" got %b", ~|zero);
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passed = 1'b0;
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end
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if (~|one !== 1'b0) begin
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$display("FAILED const. reduction ~| with input 1'b1, expected 1'b0, ",
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" got %b", ~|one);
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passed = 1'b0;
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end
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if (~|highz !== 1'bx) begin
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$display("FAILED const. reduction ~| with input 1'bz, expected 1'bx, ",
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" got %b", ~|highz);
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passed = 1'b0;
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end
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if (~|undef !== 1'bx) begin
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$display("FAILED const. reduction ~| with input 1'bx, expected 1'bx, ",
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" got %b", ~|undef);
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passed = 1'b0;
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end
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if (~^zero !== 1'b1) begin
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$display("FAILED const. reduction ~^ with input 1'b0, expected 1'b1, ",
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" got %b", ~^zero);
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passed = 1'b0;
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end
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if (~^one !== 1'b0) begin
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$display("FAILED const. reduction ~^ with input 1'b1, expected 1'b0, ",
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" got %b", ~^one);
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passed = 1'b0;
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end
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if (~^highz !== 1'bx) begin
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$display("FAILED const. reduction ~^ with input 1'bz, expected 1'bx, ",
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" got %b", ~^highz);
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passed = 1'b0;
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end
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if (~^undef !== 1'bx) begin
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$display("FAILED const. reduction ~^ with input 1'bx, expected 1'bx, ",
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" got %b", ~^undef);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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