69 lines
1.7 KiB
Verilog
69 lines
1.7 KiB
Verilog
`begin_keywords "1364-2005"
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module top;
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reg passed, in, expect;
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integer lp;
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wire rand = ∈
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wire ror = |in;
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wire rxor = ^in;
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wire rnand = ~∈
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wire rnor = ~|in;
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wire rxnor = ~^in;
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initial begin
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passed = 1'b1;
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for (lp=0; lp < 3 ; lp = lp + 1) begin
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case (lp)
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0: {in,expect} = 2'b00;
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1: {in,expect} = 2'b11;
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2: {in,expect} = 2'bzx;
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3: {in,expect} = 2'bxx;
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endcase
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#1;
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// Check the normal reductions.
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if (rand !== expect) begin
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$display("FAILED CA reduction & with input %b, expected %b, got %b",
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in, expect, rand);
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passed = 1'b0;
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end
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if (ror !== expect) begin
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$display("FAILED CA reduction | with input %b, expected %b, got %b",
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in, expect, ror);
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passed = 1'b0;
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end
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if (rxor !== expect) begin
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$display("FAILED CA reduction ^ with input %b, expected %b, got %b",
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in, expect, rxor);
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passed = 1'b0;
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end
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// Check the inverted reductions.
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if (rnand !== ~expect) begin
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$display("FAILED CA reduction ~& with input %b, expected %b, got %b",
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in, ~expect, rnand);
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passed = 1'b0;
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end
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if (rnor !== ~expect) begin
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$display("FAILED CA reduction ~| with input %b, expected %b, got %b",
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in, ~expect, rnor);
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passed = 1'b0;
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end
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if (rxnor !== ~expect) begin
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$display("FAILED CA reduction ~^ with input %b, expected %b, got %b",
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in, ~expect, rxnor);
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passed = 1'b0;
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end
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end
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if (passed) $display("PASSED");
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end
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endmodule
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`end_keywords
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