38 lines
721 B
Verilog
38 lines
721 B
Verilog
// Extracted from PR#224
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module test;
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reg clk;
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reg [3:0] ack;
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task first;
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input [1:0] p;
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begin
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@(posedge clk); $display("got posedge clk");
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`ifdef LINE_A
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//A: line below compiles under XL/NC - iverilog complains
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@(posedge ack[p]); $display("got posedge ack[p]");
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`else
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//B: line below core dumps under vvp - OK under vvm
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@(posedge ack); $display("got posedge ack");
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`endif
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@(posedge clk); $display("got posedge clk");
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$display("PASSED");
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$finish;
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end
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endtask
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initial #5 first(1);
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initial
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begin
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ack <= 0; clk <= 0;
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#10 clk <= 1;
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#10 ack <= 3; clk <= 0;
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#10 clk <= 1;
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#10 $display("FAILED");
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$finish;
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end
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endmodule // test
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