31 lines
510 B
Verilog
31 lines
510 B
Verilog
`define VUG_PCREL(u, uch) ({ {(uch - 12 - 1 > 0 ? uch - 12 - 1 : 1){u[11]}}, \
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u[10:0], 2'b00 })
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module t();
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parameter uch = 16;
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parameter u_hossz = 32;
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parameter u_prefix = 3;
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reg [u_hossz - u_prefix - 1:0] v_utas;
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reg [uch - 1:0] v_cim;
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wire [uch - 1:0] v_ugras_ide;
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assign v_ugras_ide = v_cim + `VUG_PCREL(v_utas, uch);
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initial
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begin
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v_utas = 'h0fff;
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v_cim = 'h7;
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#1;
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if(v_ugras_ide !== 'h3)
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$display("FAILED");
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else
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$display("PASSED");
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$finish;
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end
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endmodule
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