51 lines
1.1 KiB
Verilog
51 lines
1.1 KiB
Verilog
module main;
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reg passed = 1'b1;
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wire out1;
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reg local_out;
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reg mode;
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assign out1 = mode ? 1'bz : local_out;
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pullup(out1);
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initial begin
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mode = 1'b1;
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local_out = 1'bx;
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// The pull up device sets the level.
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#1 if (out1 !== 1'b1) begin
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$display("FAILED test 1, expected 1'b1, got %b", out1);
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passed = 1'b0;
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end
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mode = 1'b0;
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local_out = 1'b0;
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// Set by local out.
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#1 if (out1 !== local_out) begin
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$display("FAILED test 1, expected %b, got %b", local_out, out1);
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passed = 1'b0;
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end
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local_out = 1'b1;
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// Set by local out.
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#1 if (out1 !== local_out) begin
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$display("FAILED test 1, expected %b, got %b", local_out, out1);
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passed = 1'b0;
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end
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local_out = 1'bx;
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// Set by local out.
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#1 if (out1 !== local_out) begin
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$display("FAILED test 1, expected %b, got %b", local_out, out1);
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passed = 1'b0;
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end
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local_out = 1'bz;
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// The pull up device sets the level.
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#1 if (out1 !== 1'b1) begin
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$display("FAILED test 1, expected 1'b1, got %b", out1);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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