25 lines
311 B
Verilog
25 lines
311 B
Verilog
// Copyright 2008, Martin Whitaker.
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// This file may be copied freely for any purpose. No attribution required.
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module pr2169870();
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task automatic count;
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integer i;
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begin
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i = 0;
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while (i < 10) begin
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#1 $display("%0d", i);
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i = i + 1;
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end
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end
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endtask
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initial count;
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initial count;
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endmodule
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