15 lines
324 B
Verilog
15 lines
324 B
Verilog
module comp1001a;
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// extracted from comp1001.v,
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// Copyright (c) 2000 Paul Campbell (paul@verifarm.com)
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// GPLv2 or later blah blah blah
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reg [4:0] r170;
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initial begin
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r170 = (5'h1c % 25'h5b50) - 20'h05818;
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$displayb("r170 = ",r170);
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if (r170 == 5'b00100) $display("PASSED");
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else $display("FAILED");
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end
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endmodule
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