48 lines
778 B
Verilog
48 lines
778 B
Verilog
module signed_assignment_bug();
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reg [7:0] a;
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wire [15:0] y;
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wire [15:0] z;
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initial begin
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// Example vector
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a = 8'b10110110;
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// Wait for results to be calculated
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#1;
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// Display results
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$display("a = %b", a);
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$display("y = %b", y);
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$display("z = %b", z);
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// Finished
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$finish(0);
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end
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// Calculate signed logical OR
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manually_extended_assignment INST1(.a(a), .y(y));
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signed_assignment INST2(.a(a), .y(z));
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endmodule
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module manually_extended_assignment(a, y);
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input [7:0] a;
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output [15:0] y;
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// Manually sign extend before assignment
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assign y = {{8{a[7]}}, a};
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endmodule
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module signed_assignment(a, y);
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input [7:0] a;
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output [15:0] y;
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// $signed() sign extends before assignment
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assign y = $signed(a);
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endmodule
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