66 lines
1.8 KiB
Verilog
66 lines
1.8 KiB
Verilog
module signed_logic_operators_bug();
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reg [7:0] a, b;
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wire [15:0] yuu, yus, ysu, yss;
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wire [15:0] zuu, zus, zsu, zss;
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initial begin
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// Example vector
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a = 8'b10110110;
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b = 8'b10010010;
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// Wait for results to be calculated
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#1;
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// Display results
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$display("a = %b", a);
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$display("b = %b", b);
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$display("yuu = %b", yuu);
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$display("zuu = %b", zuu);
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$display("yus = %b", yus);
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$display("zus = %b", zus);
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$display("ysu = %b", ysu);
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$display("zsu = %b", zsu);
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$display("yss = %b", yss);
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$display("zss = %b", zss);
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// Finished
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$finish(0);
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end
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// Calculate signed logical OR
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manually_extended_logical_or INST1(.a(a), .b(b), .yuu(yuu), .yus(yus), .ysu(ysu), .yss(yss));
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signed_logical_or INST2(.a(a), .b(b), .yuu(zuu), .yus(zus), .ysu(zsu), .yss(zss));
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endmodule
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module manually_extended_logical_or(a, b, yuu, yus, ysu, yss);
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input [7:0] a, b;
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output [15:0] yuu, yus, ysu, yss;
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// Manually zero or sign extend operands before logic OR
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// - Note the operands are zero extended in "yuu", "yus" and "ysu"
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// - The operands are sign extended in "yss"
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assign yuu = {{8{1'b0}}, a} | {{8{1'b0}}, b};
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assign yus = {{8{1'b0}}, a} | {{8{1'b0}}, b};
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assign ysu = {{8{1'b0}}, a} | {{8{1'b0}}, b};
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assign yss = {{8{a[7]}}, a} | {{8{b[7]}}, b};
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endmodule
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module signed_logical_or(a, b, yuu, yus, ysu, yss);
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input [7:0] a, b;
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output [15:0] yuu, yus, ysu, yss;
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// Note that the operation is only consider signed if ALL data operands are signed
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// - Therefore $signed(a) does NOT sign extend "a" in expression "ysu"
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// - But "a" and "b" are both sign extended before the OR in expression "yss"
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assign yuu = a | b ;
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assign yus = a | $signed(b);
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assign ysu = $signed(a) | b ;
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assign yss = $signed(a) | $signed(b);
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endmodule
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