23 lines
613 B
Verilog
23 lines
613 B
Verilog
module top;
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// Check conditional generate.
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generate if (foo != "bar") initial $display("In conditional");
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endgenerate
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// Check loop generate
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generate for (lp = foo; lp < 1; lp = lp + 1) initial $display("Loop %f", lp);
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endgenerate
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generate for (lp = 0; lp < foo; lp = lp + 1) initial $display("Loop %f", lp);
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endgenerate
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generate for (lp = 5; lp < 6; lp = lp + foo) initial $display("Loop %f", lp);
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endgenerate
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// Check case generate.
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generate case (foo)
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1: initial $display("One case");
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default: initial $display("Default case");
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endcase
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endgenerate
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endmodule
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