37 lines
569 B
Verilog
37 lines
569 B
Verilog
// pr2013758
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module test;
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reg reset;
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initial begin
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// $dumpfile( "test.vcd" );
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// $dumpvars;
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reset = 0;
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#100;
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reset = 1;
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#100;
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reset = 0;
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#100 $display("PASSED");
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$finish;
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end
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submod1 s1 (.reset(reset));
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submod2 s2 (.reset(reset));
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endmodule
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module submod1(input reset);
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wire reset2 = 1;
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assign reset2 = reset;
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endmodule
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module submod2(input reset);
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always #10 @(reset)
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if (reset === 1'bx) begin
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$display("FAILED -- X escaped into sibling module!");
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$finish;
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end
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endmodule
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